;
;D16.TBL
;Instruction Table for the Doran Engineering D16/M processor.
;This table is an input to the Cross-32 meta-assembler, which
;allows it to process the D16 instructions.
;
;Revision History
;
;	1.0	Basic completed table.
;		02/10/2001. 
;
;	2.0	New addressing modes, new instructions.  
;               Full operation requires D16/M processor V. 3.0.
;                        		D16/M microcode V. 2.0. 
;               04/04/2005.    
;
;REGISTER DEFINITIONS
;None. There are no register addressing modes on the D16.
;
*
;
;OPERANDS
;There is only one type of operand on the D16, a 16-bit binary word.
;
;NUM	START	LENGTH	EXP	LOW	HIGH    ;comment
1,	16,	16,	#,	-32768,	65535   ;all operands 16 bit
;
*
;
;ADDRESSING MODES
;There are thirteen addressing modes (of seven basic types) for One Address
;Instructions. Modes 14-22 are just duplications allowing operands to appear
;in any order in the source code (for example, IX+m instead of m+IX); they
;assemble to the same object code.
;
1,{1}^03000000:			;Immediate Addressing
2,({1})^01000000:		;Direct Addressing
3,[{1}]^05000000: 		;Indirect Addressing
4,[{1}++]^0D000000:		;Post-Incremented Indirect Addressing
5,({1}+IX)^11000000:		;Direct Indexed Addressing using IX Register
6,({1}+IY)^21000000:		;Direct Indexed Addressing using IY Register
7,({1}+SP)^31000000:		;Direct Indexed Addressing using Stack Pointer 
8,[{1}+IX]^15000000:		;Indirect Indexed Addressing using IX Register
9,[{1}+IY]^25000000:		;Indirect Indexed Addressing using IY Register
10,[{1}+SP]^35000000:		;Indirect Indexed Addressing using Stack Pointer 
11,[({1}++)+IX]^1D000000:	;Post-Incremented Indirect Indexed Addr using IX
12,[({1}++)+IY]^2D000000:	;Post-Incremented Indirect Indexed Addr using IY
13,[({1}++)+SP]^3D000000:	;Post-Incremented Indirect Indexed Addr using SP
14,(IX+{1})^11000000:		;Same as mode 5, except the operands are swapped
15,(IY+{1})^21000000:		;Same as 6, except swapped 
16,(SP+{1})^31000000:		;Same as 7, except swapped  
17,[IX+{1}]^15000000:		;Same as 8, except swapped 
18,[IY+{1}]^25000000:		;Same as 9, except swapped 
19,[SP+{1}]^35000000:		;Same as 10, except swapped  
20,[IX+({1}++)]^1D000000:	;Same as 11, except swapped  
21,[IY+({1}++)]^2D000000:	;Same as 12, except swapped 
22,[IX+({1}++)]^3D000000:	;Same as 13, except swapped 
;
*
;
;INSTRUCTION MNEMONICS and OPCODES
;
;Zero Address Instructions (Implied Addressing)
;
INC ^001A:		;Increment Accumulator
DEC ^001B:		;Decrement Accumulator
COM ^001C:		;Ones Complement Accumulator (Logical NOT)
NEG ^001D:		;Twos Complement Accumulator (Twos Complement Negate)
SET ^001E:		;Set Accumulator (AC<FFFF)
CLR ^001F:		;Clear Accumulator (AC<0000)
SHL ^0020:		;Shift Left Accumulator (CF<A15, AC0<0)
LSR ^0021:		;Logical Shift Right Accumulator (AC15<0, CF<AC0)
ASR ^0022:		;Arithmetic Shift Right Accumulator (AC15<AC15, CF<AC0)
ROL ^0023:		;Rotate Left Accumulator (CF<A15, AC0<CF)
ROR ^0024:		;Rotate Right Accumulator (AC15<CF, CF<AC0)
LSW ^0025:		;Load Accumulator with Switch Register
SCF ^0026:		;Set Carry Flag (CF<1)
CCF ^0027:		;Clear Carry Flag (CF<0)
PSA ^0028:		;Push Accumulator onto Stack
POA ^0029:		;Pop Accumulator off of Stack
PSF ^002A:		;Push Flag Register onto Stack
POF ^002B:		;Pop Flag Register off of Stack
ENI ^002C:		;Enable Interrupts
DII ^002D:		;Disable Interrupts
RTN ^002E:		;Return from Subroutine
RTI ^002F:              ;Return from Interrupt, Enabling Interrupts
NOP ^0030:		;Processor No Operation
INX ^0035:		;Increment Index Register IX
INY ^0036:		:Increment Index Register IY
INS ^0037:		:Increment Stack Pointer
DEX ^0038:		;Decrement Index Register IX
DEY ^0039:		:Decrement Index Register IY
DES ^003A:		:Decrement Stack Pointer
MAX ^003B:		:Move Accumulator to Index Register IX
MAY ^003C:		:Move Accumulator to Index Register IY
MAS ^003D:		:Move Accumulator to Stack Pointer
MXA ^003E:		:Move Index Register IX to Accumulator
MYA ^003F:		:Move Index Register IY to Accumulator
MSA ^0040:		:Move Stack Pointer to Accumulator
PSX ^0041:		;Push Accumulator onto Stack
POX ^0042:		;Pop Accumulator off of Stack
PSY ^0043:		;Push Flag Register onto Stack
POY ^0044:		;Pop Flag Register off of Stack
BSW ^0045:		:Byte Swap Accumulator
BSL ^0046:		:Byte Shift Left Accumulator
BSR ^0047:		:Byte Shift Right Accumulator
BRK ^0048:		:Software Interrupt to FFFE
HLT ^00FF:              ;Processor Halt
;
;One Address Instructions
;
LDA |1-22^00010000:	;Load Accumulator
LDS |1-22^00020000:	;Load Stack Pointer 
STA |2-22^00030000:	;Store Accumulator
STS |2-22^00040000:	:Store Stack Pointer
ADD |1-22^00050000:	;Add to Accumulator
ADC |1-22^00060000:	;Add to Accumulator with Carry
SUB |1-22^00070000:	;Subtract from Accumulator
SBC |1-22^00080000:	;Subtract from Accumulator with Borrow
AND |1-22^00090000:	;Logical AND with Accumulator
ORA |1-22^000A0000:	;Logical OR with accumulator
XOR |1-22^000B0000:	;Logical Exclusive-OR with Accumulator
ISZ |2-22^000C0000:	;Increment and Skip if Zero
DSZ |2-22^000D0000:	;Decrement and Skip if Zero
JMP |1-22^000E0000:	;Unconditional Jump
JOZ |1-22^000F0000:	;Jump on Zero Accumulator
JNZ |1-22^00100000:	;Jump on Non-Zero Accumulator
JPL |1-22^00110000:	;Jump on Plus Accumulator
JMI |1-22^00120000:	;Jump on Minus Accumulator
JOC |1-22^00130000:	;Jump on Carry
JNC |1-22^00140000:	;Jump on No Carry
JOV |1-22^00150000:	:Jump on Two's Complement Overflow
JNV |1-22^00160000:	:Jump on No Two's Complement Overflow
CSR |1-4^00170000:	;Call Subroutine
LDX |1-22^00310000:	;Load Accumulator
LDY |1-22^00320000:	;Load Stack Pointer 
STX |2-22^00330000:	;Store Accumulator
STY |2-22^00340000:	:Store Stack Pointer
;
;Input and Output Instructions (One Address)
;
INP |2-22^00180000:	;Input to Accumulator
OUT |2-22^00190000:	;Output from Accumulator 
;
;end of table